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8 Mbit (x16) Multi-Purpose Flash Plus
A Microchip Technology Company
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
Data Sheet
SIX-BYTE CODE FOR BLOCK-ERASE
T BE
ADDRESSES
555
2AA
555
555
2AA
BA X
CE#
OE#
T WP
WE#
RY/BY#
T BY
T BR
DQ 15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
1434 F32.0
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
BA X = Block Address
WP# must be held in proper logic state (V IL or V IH ) 1μs prior to and 1μs after the command sequence.
X can be V IL or V IH , but no other value.
Figure 12: WE# Controlled Block-Erase Timing Diagram
SIX-BYTE CODE FOR SECTOR-ERASE
T SE
ADDRESSES
555
2AA
555
555
2AA
SA X
CE#
OE#
T WP
WE#
RY/BY#
T BY
T BR
DQ 15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
1434 F28.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. (See Table 18).
SA X = Block Address
WP# must be held in proper logic state (V IL or V IH ) 1μs prior to and 1μs after the command sequence.
X can be V IL or V IH , but no other value.
Figure 13: WE# Controlled Sector-Erase Timing Diagram
?2011 Silicon Storage Technology, Inc.
23
DS25041A
05/11
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